What is the effect of block size in cache design?

When the pc version of the spreadsheet program became available, the ibm pc quickly became the top-selling personal computer?

Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?

Assume that you have an sorted array of records. assume that the length of the array (n) is known. give two different methods to search for a specific value in this array. you can use english or pseudo-code for your algorithm. what is the time complexity for each algorithm and why?