Which memory architecture will you choose to avoid a structural hazard during simultaneous data and instruction accesses in a pipe-line?

for avoiding the structure hazards at the time of data and instruction access we can initiate

1) specific memory module

2) initiate fast cache

Explanation:

for avoiding the structure hazards at the time of data and instruction access we can initiate

1) specific memory module - it enable both writing asd reading on 1st half of clock cycle

one demerits of this is that it is expensive it required particular set of hardware to run

2) initiate fast cache

- it can separately used for both reading and writing

(http) hyper text transfer protocol

which means its an input that allows the "site" to connect with severs.