You are designing a write buffer between a write-through L1 cache and a write-back L2 cache. The L2 cache write data bus is 16 B wide and can perform a write to an independent cache address every four processor cycles.

a. How many bytes wide should each write buffer entry be?

b. What speedup could be expected in the steady state by using a merging write buffer instead of a non-merging buffer when zeroing memory by the execution of 64-bit stores if all other instructions could be issued in parallel with the stores and the blocks are present in the L2 cache?

c. What would be the effect of possible L1 misses on the number of required write buffer entries for systems with blocking and non-blocking caches?

In a heat transfer course, we can derive the equation for the temperature distribution in a flat rectangular plate. in this example, we will look at a plate at steadystate with three sides being held at t1, and one side held at t2. the temperature for any location on the plate, t(x,y), can be calculated by where create a function (prob3_5) that will take inputs of vectors x and y in feet, scalar n, scalars l and w in feet and scalars t1 and t2 in degrees fahrenheit. it will output a matrix t which is the temperature of each x and y locations. t will have the number of columns equal to the number of elements in x and rows equal to the number of elements in y. though this can be done without loops (perhaps more efficiently), your program must use a nested loop.