Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (classes A, B, C, and D). P1 with a clock rate of 2.0 GHz and CPIs of 1, 2, 2, and 1, and P2 with a clock rate of 4 GHz and CPIs of 2, 3, 4, and 4. Processor Class A Class B Class C Class D
P1 3 2 1 4
P2 2 2 2 2
Given a program with a dynamic instruction count of 1.0E5 instructions divided into classes as follows: 10% class A, 30% class B, 40% class C, and 20% class D.
1. Which implementation is faster?
2. What is the global CPI for each implementation?
3. Find the clock cycles required in both cases?