Suppose we have a processor that has a 4-way set-associative L1 cache with 256 blocks in total. Each block contains 16 bytes. The cache also stores 22 bits as tag and 4 check bits for each block. The hit time to the L1 cache is 1 cycle and the LRU policy is used for replacing cache blocks. The processor also has 8-way set-associative 4MB L2 cache with 512 blocks in total. The hit time to the L2 cache is 10 cycles and the LRU policy is used for the block replacement. (a) What is the size of the L1 cache, considering the tag and check bits