Assume that a cache miss rate (both instruction and data) is 3%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 300 cycles for each miss. Also assume that 36% of instructions are loads and stores. (or the frequency of all loads and stores in a program is 36%.) a) Assume that I is the instruction count (# of instructions). Compute the total number of cycles for memory stalls. The total number of cycles for memory stalls x I

Consider the following statements: struct nametype{string first; string last; }; struct coursetype{string name; int callnum; int credits; char grade; }; struct studenttype{nametype name; double gpa; coursetype course; }; studenttype student; studenttype classlist[100]; coursetype course; nametype name; mark the following statements as valid or invalid. if a statement is invalid, explain why.a.) student.course.callnum = "csc230"; b.) cin > > student.name; c.) classlist[0] = name; d.) classlist[1].gpa = 3.45; e.) name = classlist[15].name; f.) student.name = name; g.) cout < < classlist[10] < < endl; h.) for (int j = 0; j < 100; j++)classlist[j].name = name; i.) classlist.course.credits = 3; j.) course = studenttype.course;