You have a direct mapped cache containing 128 bytes with a cache block size of 32 bytes. The cache uses LRU replacement and write-allocate and write-back policies. Assume i and j are stored in registers, and that the array happy starts at address 0x0. Give the hit rate (as a fraction or a%) for the following two loops. Assume the cache starts out empty. #define LEAP 4 #define SIZE 64 int happy[SIZE] ; // Assume happy has been initialized to contain values. // Assume the cache starts empty at this point. for (int i = 0; i < SIZE; i += LEAP) { 11 Loop 1 happy[i] = happy[i] + i * (i + 2); } for (int j = 1; j < SIZE; j += (LEAP * 2)) { // Loop 2 happy[j] = happy[j] + j * 5; } Hit Rate for Loop 1: Hit Rate for Loop 2: b) [8 pts] For each of the changes proposed below, indicate how it would affect the hit rate of each loop above in part c) assuming that all other factors remained the same as they were in the original problem. Circle one of: "increase", "no change", or "decrease" for each loop. Loop 1: increase / no change / decrease Change associativity from direct mapped to two-way: Loop 2: increase / no change 1 decrease Loop 1: increase Change LEAP from 4 to 8: / no change / decrease Loop 2: increase / no change 1 decrease Loop 1: increase / no change / decrease Change cache size from 128 bytes to 256 bytes: Loop 2: increase / no change 1 decrease Loop 1: increase / no change 1 decrease Change block size from 32 bytes to 16 bytes: Loop 2: increase / no change / decrease