Write a Verilog/System Verilog module for a N-bit ripple carry adder. N should be parameterized and a module can be instantiated with a specific N, e. g. 8 for 8-bit, 16 for 16-bit etc.. It must use 1-bit full adders (FA) as building blocks. That means that 1-bit adder should be modeled as a Verilog/System Verilog module. Then write a test bench program to test the module using N

Write a program that uses a widgetviewer object to do the following: generate two random integers between 1 and 9 (inclusive). name one of them x, the other y. display them to the user using jlabel objects. create a jlabel object displaying the text "enter an operation number." create a jtextfield for the user's input. create a jbutton displaying the text "press here when you've entered your operation." use addandwait to add it to the widgetviewer object. when the user clicks the jbutton, evaluate operation in the following order to determine the one and only mathematical operation to perform on x and y. use a jlabel to display the result. if operation is between 1 and 10 inclusive, add x and y. if operation is evenly divisible by 4, subtract y from x. if operation is evenly divisible by 5, use integer division to divide y into x. if operation is an even number, use floating point division to divide y into x. if none of the other tests on operation apply, multiply x and y. note: operation can be negative or zero.

What are the three parts to physical security standards for various types of army equipment and the risk level

Assume that minutes is an int variable whose value is 0 or positive. write an expression whose value is "undercooked" or "soft-boiled" or "medium-boiled" or "hard-boiled" or "overcooked" based on the value of minutes. in particular: if the value of minutes is less than 2 the expression's value is "undercooked"; 2-4 would be a "soft-boiled", 5-7 would be "medium-boiled", 8-11 would be "hard-boiled" and 12 or more would be a "overcooked".