If the mask is running 5c hotter than the last mask exposure, how much hotter should the silicon wafer be than the last time it was exposed so that everything lines up as perfectly as possible? the error budget is 19 nm, the 1x reticle and chip size is 39 mm, and the thermal expansion coefficient for the silica mask and silicon wafer are 5*10^-7 and 2.6*10^-6 respectively.