Write a vhdl process for an up/down binary counter with asynchronous reset, clock enable and external load capability. you need a direction bit to choose counting up or counting down. include testbench code

process (clock, reset)

begin

if reset='1' then

count < = (others => '0');

elsif (clock='1' and clock'event) then

if clock_enable='1' then

if load_enable='1' then

count < = input;

else

if count_direction='1' then

count < = count + 1;

else

count < = count ‐ 1;

end if;

end if;

end if;

end if;

end process;