Following specifications, what is the size of l2 cache that achieves the lowest energy for the pmd (core, l1, l2, memory) for that given task? a. the core frequency is 1 ghz, and the l1 has an mpki of 100. b. a 256 kb l2 has a latency of 10 cycles, an mpki of 20, a background power of 0.2 w, and each l2 access consumes 0.5 nj. c. a 1 mb l2 has a latency of 20 cycles, an mpki of 10, a background power of 0.8 w, and each l2 access consumes 0.7 nj. d. the memory system has an average latency of 100 cycles, a background power of 0.5 w, and each memory access consumes 35 nj.

When making changes to optimize part of a processor, it is often the case that speeding up one type of instruction comes at the cost of slowing down something else. for example, if we put in a complicated fast floating-point unit, that takes space, and something might have to be moved farther away from the middle to accommodate it, adding an extra cycle in delay to reach that unit. the basic amdahl's law equation does not take into account this trade-off. a. if the new fast floating-point unit speeds up floating-point operations by, on average, 2ă—, and floating-point operations take 20% of the original program's execution time, what is the overall speedup (ignoring the penalty to any other instructions)? b. now assume that speeding up the floating-point unit slowed down data cache accesses, resulting in a 1.5ă— slowdown (or 2/3 speedup). data cache accesses consume 10% of the execution time. what is the overall speedup now? c. after implementing the new floating-point operations, what percentage of execution time is spent on floating-point operations? what percentage is spent on data cache accesses?