Assume we have a processor with a single functional unit that handles memory operations (load/store), one functional unit that handle addition, one functional unit that handles multiply operations and one functional unit that handles divisions. each functional unit can execute when the inputs to that functional unit are ready -- the performance is only limited data dependences, pipeline latencies and pipeline issue rates. the following table shows the number the latency and issue cycles for each operation: operation latency issueadd / sub 33 22multiplication 11 11division 2020 2020memory load 33 22memory store 33 22how many cycles would the following 64-bit intel code sequence take? in other words, at what cycle would the last instruction complete? movl 4(%rsp), %eax movl 8(%rsp), %edi addl %eax, %edi imull %edi, %eax movl %edi, 8(%rsp)