Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2.

Processor Class A Class B Class C Class D
P1 3 2 1 4
P2 2 2 2 2

Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D.

a. Which implementation in faster?
b. What is the global CPI for each implementation?
c. Find the clock cycles required in both cases?