Assume that a memory operation requires 4 nsec from the time a memory address value is available until one can assume a stable output value is available and that the maximum time for an address output delay from a rising edge (TAD) and the minimum data setup time prior to the falling edge of a clock pulse (TDS) are both 1/2 nsec. If a system designer wanted to be able to carry out consecutive memory operations without the need for wait states, what is the fastest clock speed (in MHz) that can support this.

1. which of the following statements are true about routers and routing on the internet. choose two answers. a. protocols ensure that a single path between two computers is established before sending packets over it. b. routers are hierarchical and the "root" router is responsible for communicating to sub-routers the best paths for them to route internet traffic. c. a packet traveling between two computers on the internet may be rerouted many times along the way or even lost or "dropped". d. routers act independently and route packets as they see fit.