You will implement three different types of FFs with two different reset types. You have to show your results on your FPGA. You have to use behavioral verilog. Steps: 1. Build a positive edge triggered TFF. 2. Add a synchronous reset to TFF. a. The reset signal should be attached to a button when you load JTAG. 3. Using a separate piece of code: Add an asynchronous reset to TFF. a. Copy and reuse your old code with some modifications.

Step 1 : For TFF with asynchronous reset, the verilog code is :

'timescale 1ns/100ps

module tff1( input t,clk,reset, output reg q );

if (reset ) begin

always at (posedge clk ) begin

q <= #4 not q;

end

end else begin

q <= 1'b0;

end

end module

Step 2 : For TFF with synchronous reset, just include reset condition inside always statement as shown :

always at(posedge clk ) begin

if ( reset ) then

q <= #4 not q;

end else begin

q <= 1,b0'

end

end

Step 3 : For developing a DFF from a TFF , you need to have a feedback loop from ouput to input . Make sure you assign the wires correctly including the signal direction . Combine both the input D and ouptut of TFF using XOR and input it to the T.

module dff (input d, clk , reset ,output reg q )

wire q;

reg t;

tff1 ( t, clk, reset , q ); //module instantiation

xor ( t,q,d);

end module

For synchronous reset , you can just replace the tff asynchronous module with synchronous module

Step 4 : For obtaining JK FF using the DFF , we just to config the 4x1 MUX such that the required output is generated

module JKFF ( input j,k ,clk, reset , output reg q)

DFF ( d ,clk, reset ,q )

reg d;

case (j,k)

when "00" then d <= q;

when "01" then d <= 1'b0;

when "10" then d <= 1'b1;

when "11" then d <= #4 not d;

default : d <= 1'bX;

end module;

no backup memory

what is inputmismatchexception?