Design a Verilog module that takes a high frequency clock input and outputs a clock signal at 1/1000 of the input frequency. The output clock signals should be 50% duty cycle, which means they should be high in half of the period and low in the other half.

// Code your design here

module clk_div

#(

parameter WIDTH = 7,// width of register

parameter N = 100// value of division here 100

)

(clk,reset, clk_out);

input clk;

input reset;

output clk_out;

reg [WIDTH-1:0] r_reg;// counting register

wire [WIDTH-1:0] r_nxt;

reg clk_track;// clock value

always at(posedge clk or posedge reset)

begin

if (reset)// reset

begin

r_reg <= 0;

  clk_track <= 1'b0;

end

else if (r_nxt == N)

   begin

  r_reg <= 0;

  clk_track <= ~clk_track;

  end

else

r_reg <= r_nxt;

end

assign r_nxt = r_reg+1;    

assign clk_out = clk_track;

endmodule

testbench:

// Code your testbench here

// or browse Examples

module clkdiv2n_tb;

reg clk,reset;

wire clk_out;

clk_div t1(clk,reset,clk_out);

initial

clk= 1'b0;

always

#5 clk=~clk;

initial

begin

#5 reset=1'b1;

#10 reset=1'b0;

#5000 $finish;

end

initial

$monitor("clk=%b,reset=%b,clk_out=%b",clk,reset,clk_out);

initial

begin

$dumpfile("dump.vcd");

$dumpvars(2);

end

endmodule

Explanation:

see waveform

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