Your L1 data cache has an access latency of 1ns, your L2 cache has an access latency of 10 ns, and main memory has an access latency of 200ns. Assume that 95% of your L1 accesses are hits, 90% of your L2 accesses are hits and that 100% of your main memory accesses are hits. What is the average memory latency as seen by the processor core?

in 2007, floridians died in alcohol-related collisions.a.  501b.  1,051c.  5,015d.  10,839

What is used to analyze and summarize your data without graphical support

Write a program in plp assembly that counts up by one starting from zero (or one) inside a loop and writes this value to the leds every time the value is increased. the memory address of the leds is 0xf0200000. the table below shows the meaning and an example usage of the instructions covered in the video, plp instructions for project 1. instruction example usage meaning load immediate li $t0, 8 register $t0 is set to the value, 8. store word sw $t2, 0($t1) the value in register $t1 is used as the memory address. the value in register $t2 is copied into this memory address. add addiu $t4, $t3, 29 register $t4 is assigned the sum of 29 and the value in register $t3. jump j your_label_name the program jumps to the line following the label, "your_label_name: ". label your label name: defines a label called "your_label_name: " that can be jumped to