Calculate the CPI, taking memory access stalls into account, given the following: CPI_ideal = 1 (this is the CPI of the processor if the memory system hit in the L1D caches) Fraction of instructions which are Load/Store: 25% L1Dhit time = N/A (already included in CPIideal) L1D hit rate = 90% L2 hit rate = 75% L2 hit time = 20 cycles DRAM access time = 100 cycles Selected 3.625 Response Feedback: Remember that only 25% of instructions access the L1D. The remaining instructions are unaffected by the memory system.