Compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution for the code below. for (i = 0; i! = j; i+ = 2)
b[i] = a[i] - a[i + 1];
When writing MIPS code, assume that variables are kept in registers as follows and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else.
i j a b c Free
R2 R8 R9 R10 R11 R3, R4, R5
A. Translate this C code to MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance.
B. If the loop exits after executing only two iterations, draw the pipeline diagram for your MIPS code executed on a 2-issue processor. Assume the processor has perfect branch prediction and can fetch any two instructions in the same cycle.
C. Re-arrange the code to achieve better performance on a 2-issue statically scheduled processor.
D. What is the speedup going from the 1-issue processor to a 2-issue processor? Assume that 1,000,000 iterations of the loop are executed. Also assume perfect branch predictions on both 1-issue and 2-issue processors.