When I say fr you say point

The reset circuit used on the four 3-bit counters analyzed in this activity reset the counts to zero (000). it makes sense for the up-counters to start at zero (000), but the down-counters should start at seven (111). what would you need to change so that the 3-bit binary down counter with j/k flip-flops you just created would reset to seven (111)?

Suppose a cpu with a write-through, write-allocate cache achieves a cpi of 2. what are the read and write bandwidths (measured by bytes per cycle) between ram and the cache? (assume each miss generates a request for one block.)

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