For each problem, below, write a single Verilog statement to achieve the desired result in the context of the standard top module of the Verilog/FPGA simulator. Use the simulator to check your work. a. Connect ss7[0] to a logic
b. Connect ss7[1] to a logic low
c. Connect ss 7[2] to a pb[0].
d. Connect ss7[3] to the complement of pb[1].
e. Connect ss7[4] to Boolean product of pb[2] AND pb[3].
f. Connect ss7[5] to Boolean sum of pb[4] OR pb[5] OR pb[6].