Write a Verilog program which implements and tests a four element cache with four bit memory addresses in three configurations (required whether or not the bonus eight-element code is provided): 1. Direct mapped, 2. Two-way set associative, and 3. Fully associative. Up to fifteen additional bonus points may be acquired by extending the program to support an eight element cache. This option would require the submission of two separate source code files.: one for the standard requirements and a second for the extension. The report must include both versions and a discussion of the differents. Both programs must build, execute, and produce correct results in order to receive any of these points. The program reads a memory trace to test the configurations and report the number of of hits and misses. A LRU mechanism must be implemented for both the two-way and fully associative configurations.