. Consider two different implementations, M1 and M2. The same instruction set is adopted, containing instruction type A, B and C with different number of cycles to complete. The instruction mixes are different on M1 and M2 though the total numbers of instructions run for a program are the same. M1 M2 Instr. CPI usage CPI usage A 2 35% 2 25% B 3 43% 5 25% C 5 22% 2 50% (1) If the clock cycle time on M1 is 1.1 times of that on M2, how many times faster is M2 than M1

Apython programming question: assume s is a string of lower case characters. write a program that prints the number of times the string 'bob' occurs in s. for example, if s = 'azcbobobegghakl', then your program should print number of times bob occurs is: 2

3. when you right-click a linked spreadsheet object, what commands do you choose to activate the excel features? a. linked worksheet object > edit b. edit data > edit data c. linked spreadsheet > edit d. object > edit data

When making changes to optimize part of a processor, it is often the case that speeding up one type of instruction comes at the cost of slowing down something else. for example, if we put in a complicated fast floating-point unit, that takes space, and something might have to be moved farther away from the middle to accommodate it, adding an extra cycle in delay to reach that unit. the basic amdahl's law equation does not take into account this trade-off. a. if the new fast floating-point unit speeds up floating-point operations by, on average, 2ă—, and floating-point operations take 20% of the original program's execution time, what is the overall speedup (ignoring the penalty to any other instructions)? b. now assume that speeding up the floating-point unit slowed down data cache accesses, resulting in a 1.5ă— slowdown (or 2/3 speedup). data cache accesses consume 10% of the execution time. what is the overall speedup now? c. after implementing the new floating-point operations, what percentage of execution time is spent on floating-point operations? what percentage is spent on data cache accesses?