Again referring back to Questions 17 and 18, assume (given the same 24-bit instruction size limitation) that, besides the instructions described in (a), there are a number of additional three-operand instructions to be implemented, for which all three operands will be in CPU registers. Detail a scheme that allows for at least 20 memory-register instructions of the type described in (a) plus at least 100 of these register-only instructions. (What bit fields, of what sizes would be required for each of the machine language instruction formats, and what would each of those bit fields represent?)