For this part of Lab you will design the sign extender module for your ARMv8 processor in Verilog. Your module should take two inputs: Instruction bits 25-0 and a two-bit control signal, and should output a 64-bit extended immediate. As an example, a rudimentary 16-to-32 bit sign extender is below. module SignExtender(BusImm, Imm16, Ctrl);
output (31:0] BusImm;
input (15:0] Imm16;
input Ctrl;
wire extBit;
assign #1 extBit = (Ctrl ? 1'be : Imm16[15]);
assign BusImm = {{16{extBit}}, Imm16};
endmodule
Re-write this module to meet the needs of your ARMv8 processor. Depending on the control signal, it should extend the right set of bits in the instruction up to a full 64-bits. Save this module in a file called SignExtender. v. You may determine how the control signal maps to the functions of the sign extender, but your sign extender should support the following: I-type instructions (ADD, SUB), D-type instructions (LDUR, STUR), B, and CBZ.
Implement a testbench for the module, SignExtender, and simulate the testbench with iVerilog. Your testbench should be self-checking, i. e. it should not only set inputs but it should also check for expected outputs and print a failure message in the event of unexpected output. You may use the testbenches provided in Lab06 as an example of an exhaustive, self-checking testbench. Simulate your testbench and show that your new SignExtender works properly.