Computers and Technology, 27.08.2021 20:40 taryn3

This problem relates to a version of our MIPS processor that still employs 32-bit memory words and 32-bit CPU registers, but uses 24-bit virtual addresses and 16-bit physical addresses. The page size used for the system is 8192 bytes and virtual address translation is performed using an inverted page map table. On this system, only one program or process at a time is allowed to be in memory so each page table entry only contains a page number followed on the right by a dirty bit and valid bit. The system also contains L1 instruction and data caches; but no other caches. The data cache contains 512 cache lines and has a 2-way set associative organization with a line size of 64 bytes. The caches are accessed using physical addresses. All cache management information is held in a separate cache directory. Shown below is the current contents of the first eight PTEs in the inverted page map table:
PTE # PTE contents in hex
0 0x103A
1 0x0249
2. 0x153D
3 0x0057
4 0x12AB
5 0x16C2
6. 0x02E3
7 0x1799
a) What is the total number of bits required for the entire data cache to implement a true LRU replacement policy?
b) Which set, if any, in the data cache is accessed due to executing the two instructions:
lui $t2,0x17
lw $t3,0x644($t2)
c) If the following instructions are currently in memory, explain why they do or do not cause a page fault when they are executed.
lui $t2,0xF6
lw $t3,0 ($t2)

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This problem relates to a version of our MIPS processor that still employs 32-bit memory words and 3...

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