Consider two threads, T1 and T2, with the following codes ($zero represents a register that is hardwired to value "0"): T1
my_again:
lw r2, 0(r1)
lw r4, 4(r1)
add r2, r2, r8
add r4, r4, r8
sw r2, 4(r1)
sw r4, 0(r1)
sub r1, r1,-4
bne r1, $zero, m
Each of these threads is to be separately scheduled and executed on a two-slot VLIW machine with the goal of achieving a minimum number of cycles. A bundle in this architecture has two instructions. The first of these instructions can be only an ALU or branch instruction, whereas the second one can be only a load or store instruction. You are allowed to reorder independent instructions and change the offset of addressing (if needed). You are not allowed to combine instructions.
5-a: Map T1 to this VLIW machine. Explain each instruction-to-execution slot mapping decision you make in sufficient detail (i. e., why you have decided so, couldn’t instruction be scheduled in an earlier slot (cycle)?).
5-b: Map T2 to this VLIW machine. Explain each instruction-to-execution slot mapping decision you make in sufficient detail (i. e., why you have decided so, couldn’t instruction be scheduled in an earlier slot (cycle)?)
5-c: Repeat 5-a, but this time assuming that any instruction can be mapped to any execution slot.
5-d: Repeat 5-b, but this time assuming that any instruction can be mapped to any execution slot.
Now, you decided to move to a fine-grain multi-threaded architecture (FGMT). The FGMT architecture you are considering can execute up to 4 instructions in parallel. Further, in a given cycle, any combination of independent instructions can be executed in parallel.
5-e: Show a scheduling of these two threads together on the FGMT machine with the goal of improving throughput.