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a. Extract the setup time TSU, hold time Thold, clock-to-Q delay TC2Q, and D-to-Q delay TD2Q, by sliding the edge of D relative to the clock edge. TSU and Thold can be obtained when TD2Q is 5% higher than the correct value. Question 1: Which clock edge should be used in these simulations, rising or falling? Question 2: What are the values of TSU, Thold, TC2Q, and TD2Q? b. Use CL=5fF to re-extract the timing. Question 3: Are they different from the answers in a? How do you re-design the latch so that TC2Q is relative independent on CL? Draw your schematics and verify

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