When do diminishing marginal returns occur ?

Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?

Idon understand these and need some ! ?

Design a pos circuit that displays the letters a through j on a seven-segment indicator. the circuit has four inputs w, x, y, and z which represent the last 4 bits of the uppercase ascii code for the letter to be displayed. thus, if wxyz = 0001 then "a" will be displayed. (any answer with 22 or fewer gates and inverters, not counting any for the inputs, is acceptable)