Suppose we have 16 bit byte-addresses and the clock frequency is 2ghz. we have the cache parameters as follows: cache size: 4kib block size: 1 word (4 bytes) cache hit time: 2 cycles cache miss penalty: 100 cycles direct mapped cache now suppose we access the following addresses, in order: 0x, 0x0004, 0x0008, 0x000c, 0x1000, 0x1004, 0x1008, 0x100c, 0x, 0x0004, 0x0008, 0x000c q1.13 points what are the widths of the tag, index, and offset fields (in # bits)? tag field size?