Amulti-level cache has a l1 hit time of 1 clock cycle, an l1 miss penalty of 19 clock cycles, and an l2 miss penalty of 196 clock cycles. if 4% of accesses to l1 miss and 4% of accesses to l2 miss, what is the average memory access time (amat)? calculate your answer to one decimal place.

x+2 because it just doubles hon so the pattern can actually tell you the expression.

so for example,

if x=2 then 2+2 is 4

if x=4 then 4+4 is 8

and so on and so forth.

i really hope that this makes sense and you out in a way hon: )

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i don't understand really? can u provide more information

u should make a machine that can make ice cream fresh!

sorry what a asnns

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