Design a synchronous sequential circuit with two inputs, a and b, one output, z, and a clock input, clk. the circuit is to change states only on the rising edge of the clock.
the circuit is to be designed as a mealy model, and is to behave as follows:

1. on reset, z=0.
2. whenever z=0, z changes to 1 if and only if, while a=1, the values of b at two
consecutive clock transitions are 0-1 (in that order). z should change as soon as b becomes 1 in the second clock period.
3. whenever z=1, z changes back to 0 if and only if, while b=0, the values of a at two consecutive clock transitions are 0-1. z should change as soon as a becomes 1 in the second clock period.
(hint: this should require four states.)

show all steps of the design process, beginning with a state diagram and showing how circuit equations are derived from it. implement the design two ways, one using d flip flops and one using jk flip flops, sketching the schematic diagram of each solution.