Write an HDL code for an 32-bit Universal Shift Register with a positive-edge sensitive clock, a synchronous enable (highest priority), and an asynchronous negative-edge sensitive reset. The register can be loaded with serial in (1-bit) or parallel in (32-bit), and can be read serially (1-bit) or in parallel (32- bit). Also the register can perform left or right shift with a selection bit (1 for left shift, and 0 for right shift). b) Write a testbench for the module you wrote in (a) to test all of the corner cases.