Suppose we wish to implement the two logic functions given by: F = A + B + C and G = A + B + C + D Assume both true and complementary signals are available.

(a) Implement these functions in dynamic CMOS as cascaded  stages so as to minimize the total transistor count
(b) Design an np-CMOS implementation of the same logic functions. Does this design display any of the difficulties of part (a)?

An electric motor is used to drive a power press which makes steel turning moment diagrams 323 pressings from a metal sheet. the motor runs at a mean speed of 50 rev/s. the torque required is 10.0nm for 0.2s, followed by 1.0nm for0.3 s with this sequence then being repeated. what is the minimum power required of the motor and the moment of incrtia required for the t1ywhcel if the speed fluctuations are to be restricted to 1.5%?