Write a Verilog module that describes 8-bit right shifter register with control signals A(arithmetic), L(logical), CLR(clear) and LD(load). Input signals are CLK, LD and 8-bit input D. Output signal is 8-bit output Q. CLR signal will clear Q. LD signal will load input D to Q. A signal will do arithmetic right shift of Q, while L signal will do logical right shift of Q.

Ashielded metal arc-welding operation is accomplished in a work cell by a fitter and a welder. the fitter takes 5.5 min to load components into the welding fixture at the beginning of the work cycle, and 1.5 min to unload the completed weldment at the end of the cycle. the total ength of the weld seams 1200 mm, and the travel speed used by the welder averages 300 mm/min. every 600 mm of seam length, the welding stick must be changed, which takes 0.8 min. while the fitter is working, the welder is idle (resting): and while the welder is working the fitter is idle. (a) determine the average arc-on time as a fraction of the work cycle time. (b) how much improvement in arc-on time would result if the welder used flux-cored arc welding (manually operated), given that the spool of weld wire must be changed every 10 weldments, and it takes the welder 5.0 min to accomplish the change? (c) what are the production rates for these two cases (weldments completed per hour)? attach your work and solutions.