1. Write the VHDL statement to declare a 5-bit signal with indices 4 downto 0. Name the signal tempSum. 2. Write the VHDL statement to describe a 4-bit adder. Use the addition operator Assume that two 4-bit input ports, A and B, have been declared in the Entity statement Use these ports as inputs to the adder. Use the signal tempSum as the output from the adder Note that the width of the adder circuit synthesized (and implemented) from the VHDL code is equal to the width of the larger signal being added. In this case, both A and B are 4-bit signals Consequently, the adder circuit implemented will be four bits wide. However, we need to produce a 5-bit result so that we can obtain the 4-bit sum and the carry-out.
3. Modify the VHDL statement written above to describe a 5-bit adder circuit Hint: use the concatenation operator and the binary value O' with one or both of the input ports Assume that sum has been declared in the Entity statement. Assume that carry- out has been declared in the Entity statement addition operator with signals of type STD LOGIC or STD LOGIC. VECTOR. Provide your answer
4. Write the VHDL statement to assign bits 3 downto 0 of tempSum to the 4-bit port sum
5. Write the VHDL statement to assign bit 4 of tempSum to the port carry - out
6. Identify the package (or packages) that must be included in your VHDL code in order to use the below.