Given an input of a 9-bit Boolean vector M, write a SystemVerilog (SV) model for the detector specified as follows. If the number of the logic high bits of M equals the first digital of the PSU ID number of one member of your group, the detector will give logic high, otherwise low. 2.1) Write a SV algorithmic model (always_comb) of the detector having a delay of 10ns.
2.2) Write a SV dataflow model (continuous assignments) of the detector having a delay of 10ns.
Using the same testbench to simulate both designs. Your testbench should cover 512 combinations of the 9-bit vector, list all matched result in a log file with "#RUN_TIME, VECTOR STRING, MATCHED"