Consider implementation of an n-bit shift register with parallel load capability (its operation table is given in lecture notes set 4, p.45) using the 22v10 pal complex programmable logic device. (a) show the next-state equations for the first bit and for the last bit of the shift register. (b) what is the largest size shift register (max value of n) that can be implemented using single 22v10 pal? bidirectional shift register with parallel load parallel outputs аз ag ai cleara clk 4×1 mux 4x1 4x1 mux mux mux 3210 3210 3 2 10 serial serial input for o shift-left input for ㅡㅡ shift-right 13 parallel inputs function mode controlled by si so 0 0 no change 0 1,shift right 1 0 shift left 1 1 parallel load (available as msi device)