Computer architecture1.your company has just bought a new intel core i5 dual- core processor, and you have been tasked with optimizing your software for this processor. you will run two applications on this dual core, but the resource requirements are not equal. the first application requires 80% of the resources, and the other only 20% of the resources. assume that when you parallelize a portion of the program, the speedup for that portion is 2.[10] < 1.10> given that 40% of the first application is parallelizable, how much speedup would you achieve with that application if run in isolation? [10] < 1.10> given that 99% of the second application is parallelizable, how much speedup would this application observe if run in isolation? [20] < 1.10> given that 40% of the first application is parallelizable, how much overall system speedup would you observe if you parallelized it? [20] < 1.10> given that 99% of the second application is parallelizable, how much overall system speedup would you observe if you parallelized it?

To display data in a certain manner like alphabetical order is called

Problems: 1. using textbooks, reference books, and internet as your source of research, draw the following microprocessor microarchitectures i. intel 8086 ii. motorola 68000 i atmel atmega32 iv. mips single cycle v. arm cortex-m3 write an hdl module for a hexadecimal seven-segment display decoder. the input is 4-bit binary representing a hex number (0-f), and the output is 8-bit seven segment display bits (a-h). thus, the decoder must handle the digits 10 - 15 to display a-f respectively, in addition to 0-9 numbers. 2. design a 4-bit left and right rotator (both outputs). first sketch schematic diagrams of your design. then implement your design using hdl coding. 3. 4. design a modified priority encoder that receives an 8-bit input, a7: 0 and produces a 3-bit output, y2o. y indicates the most significant bit of the input that is true. y should be 0 if none of the inputs are true. give a simplified boolean equation, sketch a schematic, and write an hdl code. 5.write an 8: 1 multiplexer module called mux8 with selection inputs s, data input d, and data output y. data input (d) and data output (v) are 32-bit wide

Wich technology can a website use to allow you to listen to a concert live over the internet?