The chief architect now needs to design a memory with an addressability of 32 bits. Suppose the architect can only use the same number of total bits as a 219x4 memory has. What will be the address space of the new memory

The question is incomplete, the correct question is:

>The chief architect is in the process of designing a company new processor has drafted an Isa that includes many operations. AND, SUBSTRACTION, OROr, XOR, NAND, NOR, NOT. TgeThe total number of copies is 34. The chief architect suggested having 14 registers in the register file. Since the instruction might require 3 registered operands, we need k bit for the instruction where k> or = (34×14×14×14), thus k=17 bits.

In a few sentence, explain to the architect while eliminating a few of the opcodes and allowing 16 registers a better choice in terms of micro architecture. For credit, your response must allow for 14-bit instructions. Be specific about which opcodes should be eliminated.

The chief architect now needs to design a memory with an addressability of 32 bits. Suppose the architect can only use the same number of total bits as a 219x4 memory has. What will be the address space of the new memory

K=18 bits.

Explanation:

The total number of opcode is given by Opcode= 2^|opcode field|

The total number of Opcode is 34

34= 2^|opcode field|

ln(34)= |opcode field| ln(2)

|Opcode field|= ln (34)/ In (2) = 5.088

For instance,

If we choose opcode field as 5, the total number of opcode is 2^5=32

If we choose opcode field as 6, the total number of opcode is 2^6= 64

As chief architect uses 34 opcodes, he chooses opcode field as 5 and eliminates 2 opcodes.

The maximum number to be registered is given as Regmax= 2^|registered field|

If chief architect allows 14 registers,

14= 2^|registered field|

|registered field|=4

To represent 14 registers, 4 bits are required.

So, instead of choosing opcode as 6, if the chief architect uses 5 as Opcode field and uses 14 registers, 30 registered fields which are used with Opcode field will be saved.

Therefore, the two codes to be eliminated are NAND and NOR as this operagion can be performed using AND, OR and NOT.

If the chief architect uses 32-bits, he can use opcode field bits as 5.

The address space of the new memory is given as:

K=log2(32×19×19×19)= log2(219488) = 17.7438

K=18bits